The present invention relates generally to detection of defects in memory cell array devices, such as, but not limited to, non-volatile memory cell arrays.
Memory cell arrays, such as non-volatile memory (NVM) cell array devices, may comprise a plurality of memory cells connected to word lines and bit lines. For example, FIG. 1 illustrates a typical memory cell (virtual ground) array 10. A plurality of memory cells 12, such as, but not limited to, NVM cells, e.g. nitride, read-only memory (NROM) cells, may be connected to local bit lines 14 and to word lines 16. The local bit lines 14 may be connected to global bit lines 18 via select transistors 20. The array 10 may be divided into one or more isolated slices 22 by means of isolation zones 24. The isolated slices 22 may be segmented in the bit line direction by select transistors 20, and the select transistors 20 may be arranged in distinct areas in the array 10. This segmentation creates isolated physical sectors. More than one physical sector may share the same global bit lines 18. Memory cells 12 in physical sectors that share the same global bit lines 18 may not interact due to the isolating select transistors 20.
The amount of data accessible with the array 10 may include xe2x80x9cblocksxe2x80x9d of data. A xe2x80x9cblockxe2x80x9d is defined as a basic amount of data containing a certain amount of bytes. For example, a block may contain 256 bytes (256B), 512B, 528B or any other number of bytes.
In array 10, read and program operations may be performed in a block granularity, i.e., on a single block. Erase operations may be performed on a single block or groups of blocks. Such groups of blocks are defined as xe2x80x9cerase sectorsxe2x80x9d (E-sectors). For example, an E-sector may contain 8 blocks, 32 blocks or 64 blocks or any other number of blocks.
During the manufacture of such arrays, certain defects may occur, examples of which are now explained.
As indicated by reference line 31, one local bit line 14 may become electrically shorted to another local bit line 14. Any memory cells connected to the shorted local bit lines are prone to fail due to this short. This defect may further affect the operation or performance of other memory cells within the particular isolated slice where the local bit lines short 31 occurred.
As indicated by reference line 32, a local bit line 14 may have an open circuit, e.g., due to a cut in the line or an improperly formed line, or due to improperly formed or missing contact with select transistors. Any memory cells connected to the open local bit line are prone to fail due to this open. This defect may further affect the operation or performance of other memory cells within the particular isolated slice where the local bit line open 32 occurred.
As indicated by reference line 33, one global bit line 18 may become electrically shorted to another global bit line 18. This defect may affect all the memory cells within the isolated slices of any physical sectors connected to the shorted global bit lines. If the global bit lines that are shorted to one another belong to two different isolated slices, then the operation or performance of memory cells within isolated slices that share the shorted global bit lines may be affected.
As indicated by reference line 34, a global bit line 18 may have an open circuit, e.g., due to a cut in the line or an improperly formed line, or due to improperly formed or missing contact with select transistors. This defect may affect the operation or performance of memory cells within all the isolated slices connected to the open global bit line.
As indicated by reference line 35, a word line 16 may become electrically shorted to another word line 16. This may be due to an electrical short in the formation of the material of the word line. Any memory cells connected to the shorted word lines are prone to fail due to this short. This type of defect may further affect the operation or performance of memory cells in other word lines that may be operative with the defective word lines (e.g. a word line that corresponds to the same erase sector as the defective word line).
As indicated by reference line 36, a word line 16 may have an open circuit, e.g., due to a cut in the line or an improperly formed line, or due to an improperly formed or missing electrical contact. This defect may affect the operation or performance of memory cells along the open word line, and may further affect memory cells on other word lines that may be operative with the defective word line (e.g. a word line that corresponds to the same erase sector as the defective word line).
As indicated by reference line 37, a word line 16 may become electrically shorted to a local or to a global bit line 14. This may be due to an electrical short in the formation of the materials of the word line 16 and of the local bit line 14 or the global bit line 18. This defect may affect the operation or performance of memory cells within the isolated slice where the short 37 occurred, of memory cells along the word line where the short 37 occurred, and of memory cells on other word lines that may be operative with the word line where the short 37 occurred (e.g. a word line that corresponds to the same erase sector as the defective word line).
The relative probability of the occurrence and types of defects depends on, inter alia, the manufacturing process details (e.g., etching procedures), on the line widths and spacing, on the technology design rules and on structural dimensions (e.g., intra layer dielectric thickness). Detection of structural defects as those presented above by reading, programming and erasing each of the memory cells is very time consuming. Furthermore, any trimming or tuning procedure per device that is required and which involves accessing memory cells (e.g., a reference cell programming operation relative to memory array cells), can only be performed if the structural defects have been identified and replaced upfront. Otherwise, the trimming or tuning results may be inaccurate or incorrect. Thus, an improved and time efficient method for structural defects detection is desired.
The present invention seeks to provide an improved method for detection of defects in memory cell array devices, such as, but not limited to, non-volatile memory cell arrays. The method may employ a simple defect detector added to the circuitry of the memory cell array, which may provide defect detection with logic circuitry and truth tables, as described more in detail hereinbelow.
There is thus provided in accordance with an embodiment of the present invention a method for defect detection, comprising providing a memory cell array comprising memory cells connected to word lines and local bit lines, and global bit lines connected to the local bit lines, the global bit lines comprising at least two portions, one portion connected to a voltage source, and the other portion connected to a defect detector, the defect detector comprising logic circuit components for outputting a logic signal, and detecting a defect comprising at least one of a short circuit and an open circuit in at least one of the word lines, local bit lines and global bit lines by detecting a signal at the defect detector.
In accordance with an embodiment of the present invention the detecting comprises detecting a short circuit between a pair of the global bit lines by:
a. driving a first portion of the global bit lines by the voltage source to a first voltage level,
b. discharging a second portion of the global bit lines connected to the defect detector to a second voltage level,
c. preventing any substantial conduction path between the two portions of global bit lines,
d. disabling the discharging of the second portion of global bit lines connected to the defect detector, and
e. detecting a signal at the defect detector and determining if there is a defect in accordance with the signal.
Further in accordance with an embodiment of the present invention the determining comprises determining that there is a short circuit between the global bit lines if the signal is above a predefined threshold.
Still further in accordance with an embodiment of the present invention the preventing comprises driving the word lines of memory cells operative with the at least two portions of global bit lines to a level that maintains the memory cells in a substantially non-conducting state.
In accordance with an embodiment of the present invention the preventing comprises driving the select transistors which connect the two portions of global bit lines to local bit lines to a level that maintains the select transistors in a substantially non-conducting state.
Further in accordance with an embodiment of the present invention the first and second portions of global bit lines are arranged such that in any pair of adjacent global bit lines one corresponds to the first portion and the other to the second portion.
Still further in accordance with an embodiment of the present invention the signal is relative to the voltage level of the second portion of global bit lines connected to the defect detector.
Further in accordance with an embodiment of the present invention the first voltage level is a positive voltage and the second voltage level is a close to ground voltage.
In accordance with an embodiment of the present invention the detecting comprises detecting a short circuit between a pair of the local bit lines by:
a. driving a first portion of the local bit lines by the voltage source to a first voltage level,
b. driving the word lines of memory cells operative with the at least two portions of local bit lines to a level that maintains the memory cells in a substantially non-conducting state,
c. discharging a second portion of the local bit lines connected to the defect detector to a second voltage level,
d. disabling the discharging of the second portion of local bit lines connected to the defect detector, and
e. detecting a signal at the defect detector and determining if there is a defect in accordance with the signal.
In accordance with an embodiment of the present invention the determining comprises determining that there is a short circuit between the local bit lines if the signal is above a predefined threshold.
Further in accordance with an embodiment of the present invention the signal is relative to the voltage level of the second portion of local bit lines connected to the defect detector.
Still further in accordance with an embodiment of the present invention the first and second portions of local bit lines are arranged such that in any pair of adjacent local bit lines one corresponds to the first portion and the other to the second portion.
Further in accordance with an embodiment of the present invention the first voltage level is a positive voltage and the second voltage level is a close to ground voltage.
In accordance with an embodiment of the present invention the detecting comprises detecting an open circuit in one of the local or global bit lines by:
a. driving a first portion of the local and global bit lines by the voltage source to a first voltage level,
b. driving at least one word line of memory cells operative with the portions of local and global bit lines to a level that maintains the memory cells in a substantially conducting state,
c. discharging a second portion of the local and global bit lines connected to the defect detector to a second voltage level,
d. disabling the discharging of the second portion of local and global bit lines connected to the defect detector, and
e. detecting an signal at the defect detector and determining if there is a defect in accordance with the signal.
Further in accordance with an embodiment of the present invention the determining comprises determining that there is an open circuit in one of the local or global bit lines if the signal is not above a predefined threshold.
Still further in accordance with an embodiment of the present invention the signal is relative to the voltage level of the second portion of global bit lines connected to the defect detector.
In accordance with an embodiment of the present invention the first voltage level is a positive voltage and the second voltage level is a close to ground voltage.
Further in accordance with an embodiment of the present invention each of the portions of local and global bit lines consist of a single global bit line and a single local bit line.
Still further in accordance with an embodiment of the present invention the first and second portions of local and global bit lines are arranged such that in any pair of adjacent local bit lines one corresponds to the first portion and the other to the second portion, and in any pair of adjacent global bit lines one corresponds to the first portion and the other to the second portion.
In accordance with an embodiment of the present invention the detecting comprises detecting a defect in one of the word lines by:
a. driving at least one of the word lines to a level that maintains the memory cells on that word line in a substantially conducting state,
b. driving a first portion of the global and local bit lines by the voltage source to a first voltage level, discharging a second portion of the global and local bit lines connected to the defect detector to a second voltage level,
c. disabling the discharging of the second portion of global bit lines connected to the defect detector, and
d. detecting a signal at the defect detector and determining if there is a defect in accordance with the signal.
In accordance with an embodiment of the present invention the portions of local and global bit lines are placed close to the beginning and close to the end of the word line.
Further in accordance with an embodiment of the present invention each of the second portions of global bit lines placed close to each of the word line ends are connected to a defect detector.
Still further in accordance with an embodiment of the present invention the portions of local and global bit lines placed close to the beginning and close to the end of the word line are arranged such that in any pair of adjacent local bit lines one corresponds to the first portion and the other to the second portion, and in any pair of adjacent global bit lines one corresponds to the first portion and the other to the second portion.
In accordance with an embodiment of the present invention the determining comprises determining that there is at least one of an open circuit and a short circuit in one of the word lines if the signal of the defect detector connected to bit lines close to at least one end of one of the word lines is not above a predefined threshold.
There is also provided in accordance with an embodiment of the present invention apparatus for defect detection, comprising a memory cell array comprising memory cells connected to word lines and local bit lines, global bit lines connected to the local bit lines, the global bit lines comprising at least two portions, one portion connected to a voltage source, and the other portion connected to a defect detector, the defect detector comprising logic circuit components for outputting a logic signal.
In accordance with an embodiment of the present invention each of the portions of the global bit lines or local bit lines may be driven simultaneously or separately.
Further in accordance with an embodiment of the present invention one of the portions of the global bit lines comprises even global bit lines and the other portion of the global bit lines comprises odd global bit lines.
Still further in accordance with an embodiment of the present invention one of the portions of the local bit lines comprises even local bit lines and the other portion of the local bit lines comprises odd local bit lines.
In accordance with an embodiment of the present invention the portions of local or global bit lines are arranged such that in any pair of adjacent local bit lines one corresponds to the even portion and the other to the odd portion, and in any pair of adjacent global bit lines one corresponds to the even portion and the other to the odd portion.
Further in accordance with an embodiment of the present invention the portion of the global bit lines that is connected to the defect detector is also connected to a discharge transistor.
In accordance with an embodiment of the present invention a processor is adapted to process logic signals from the defect detector.
Further in accordance with an embodiment of the present invention the connections are electrical connections through at least one conducting transistor.